Design Engineer for Test
Description
Job Description:�
Do Something Wonderful
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Are you passionate about working on the latest and greatest process nodes? Then the Foundry Technology Enabling group at Intel has opportunities for you. We are looking for a DFT Engineer to join our team who is ready to make significant impacts on the future designs at Intel.
As a member of the Design for Test and Quality team you will be responsible for but not limited to the following activities:
You will work on the design, RTL, and RTL/GLS validation, in the following DFT domains: TAP Controller, Scan/ATPG, Array DFT (MBIST).
You will also contribute or be involved with trace pattern generation efforts as well as post-silicon enabling debug support and/or analysis of the DFT features and content types you are responsible for.
Behavioral skills we are looking for:
Strong communication skills.
Leadership willingness in driving execution.
Strong teamwork, problem solving and influencing skills.
Willingness to work with different geographical locations.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
- Bachelor?s degree in electrical/computer engineering or related STEM degree with 7+ years of industry experience in at least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST)
Preferred Qualifications:
- Master's in electrical/computer engineering or related STEM degree with 5+ years of industry experience in:
EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring up preferably Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug
Knowledge of ATPG, various fault models, fault grading
Knowledge of iJTAG/TAP architecture
DFT logic generation, integration, and verification
EDA tools such as ATPG tools, Siemens Tessent Shell, Synopsis VCS simulation and/or debug tools
Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer
Post Silicon/ATE Bring-Up Support
Experience with RTL (Verilog, System Verilog, VHDL)
Experienced HireShift:
Shift 1 (United States of America)Primary Location:�
US, California, FolsomAdditional Locations:
US, California, Santa Clara, US, Oregon, HillsboroBusiness group:
Intel's Sales and Marketing (SMG) organization works with global customers and partners to solve critical business problems with Intel based technology solutions. SMG works across business units to amplify the customer voice and deliver solutions that accelerate their business. We work across numerous industries, including retail, enterprise and government, cloud services and healthcare as examples. The operations team focuses on forecasting, driving alignment with factory production and delivering efficiency tools and our marketing capability drives demand and localized marketing in locations around the globe. Our sales force navigates a complex partner and customer ecosystem while shaping product roadmaps, driving value for our customers, and collaborating to harness emerging technology trends to deliver comprehensive solutions.Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. �Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in
US, California:$123,419.00-$185,123.00Salary�range�dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.